Implementation of 24 Bit Multiplier Using Parallel Multiplication with Sorting Based Binary Counters for VLSI Applications

EasyChair Preprint 8653

Abstract

This project consists of an innovative way of rapid counters such as (7, 3), (15, 4) etc., binary counters and approximate (4:2) compressors which is based on sorting network. For improving the speed, a high compressor counters need to be employed. The counter inputs are divided asymmetrically into two pieces and then fed into sorting networks as inputs to construct sequences that are represented solely by one-hot code sequences. We can develop and further refine the (7, 3) counter using this method, which outperforms alternative designs in terms of latency, overall area, and power consumption in the vast majority of circumstances. A (15, 4) counter is developed, and it has a lower latency despite using less power and taking up less space. In addition, using a sorting network, we create approximation compressors (4:2). They built an 8 x 8, 16 x 16 bit multiplier to examine the performance of the circuits they constructed. A 24Bit multiplier is made and the effectiveness of the design is synthesized and simulated using Xilinx Vivado.

Keyphrases: 24 bit multiplier, Binary counters, approximate 4:2 compressor, one-hot code, sorting network

@booklet{EasyChair:8653,
  author    = {Pinniboyina Anand Venkat Seshu Babu and K. Rajasekhar},
  title     = {Implementation of 24 Bit Multiplier Using Parallel Multiplication with Sorting Based Binary Counters for VLSI Applications},
  howpublished = {EasyChair Preprint 8653},
  year      = {EasyChair, 2022}}