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Simulation Based Evaluation of Bit-Interaction Side-Channel Leakage on RISC-V Processor

16 pagesPublished: October 3, 2022

Abstract

Masking is a promising countermeasure against side-channel attack, and share slic- ing is its efficient software implementation that stores all the shares in a single register to exploit the parallelism of Boolean instructions. However, the security of share slicing relies on the assumption of bit-independent leakage from those instructions. Gao et al. recently discovered a violation causing a security degradation, called the bit-interaction leakage, by experimentally evaluating ARM processors. However, its causality remained open because of the blackbox inside the target processors. In this paper, we approach this problem with simulation-based side-channel leakage evaluation using a RISC-V processor. More specifically, we use Western Digital’s open-source SweRV EH1 core as a target plat- form and measure its side-channel traces by running logic simulation and counting the number of signal transitions in the synthesized ALU netlist. We successfully replicate the bit-interaction leakage from a shifter using the simulated traces. By exploiting the flexi- bility of simulation-based analysis, we positively verify Gao et al.’s hypothesis on how the shifter causes the leakage. Moreover, we discover a new bit-interaction leakage from an arithmetic adder caused by carry propagation. Finally, we discuss hardware and software countermeasures against the bit-interaction leakage.

Keyphrases: bit interaction leakage, masking, risc v, share slicing, side channel attack, simulation

In: Ulrich Kühne and Fan Zhang (editors). Proceedings of 10th International Workshop on Security Proofs for Embedded Systems, vol 87, pages 18-33.

BibTeX entry
@inproceedings{PROOFS2021:Simulation_Based_Evaluation_Bit,
  author    = {Tamon Asano and Takeshi Sugawara},
  title     = {Simulation Based Evaluation of Bit-Interaction Side-Channel Leakage on RISC-V Processor},
  booktitle = {Proceedings of 10th International Workshop on Security Proofs for Embedded Systems},
  editor    = {Ulrich Kühne and Fan Zhang},
  series    = {EPiC Series in Computing},
  volume    = {87},
  publisher = {EasyChair},
  bibsource = {EasyChair, https://easychair.org},
  issn      = {2398-7340},
  url       = {/publications/paper/2hsn},
  doi       = {10.29007/5wq7},
  pages     = {18-33},
  year      = {2022}}
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