Multi-Start Simulated Annealing for FPGA Floorplanning with Partially-Reconfigurable Regions

EasyChair Preprint 797

Abstract

In the integrated circuit design flow for FPGA, floorplanning may be very useful prior to the place and route stage, in order to make it easier to get an initial placement of good quality. It consists in finding a satisfactory placement of pre-determined regions of the circuit on the resource matrix that composes the FPGA hardware, minimizing the distance between the regions that communicate with each other, as well as between the regions and the input/output ports connected to them. To this difficult problem can be added additional constraints, such as taking into account partially reconfigurable regions.

We present the method we proposed for the RAW Floorplanning Design Contest, held on the occasion of the 25th anniversary of the Reconfigurable Architectures Workshop (RAW), held in conjunction with the IPDPS'18 conference. The solution method is a multi-start simulated annealing procedure, which won first place in the contest.

Keyphrases: FPGA, Floorplanning, Simulated Annealing, multi-start

@booklet{EasyChair:797,
  author    = {Francois Galea and Sergiu Carpov and Lilia Zaourar},
  title     = {Multi-Start Simulated Annealing for FPGA Floorplanning with Partially-Reconfigurable Regions},
  howpublished = {EasyChair Preprint 797},
  year      = {EasyChair, 2019}}